Jekyll2026-06-06T23:30:55+00:00https://uoftasic.com/feed.xmlUofT ASIC TeamWebsite of the UofT ASIC Team. Practical IC design opportunities, open-source silicon, and resources for undergraduates at the University of Toronto.UofT ASIC TeamSimProc: TinyTapeout2025-11-10T00:00:00+00:002025-11-10T00:00:00+00:00https://uoftasic.com/blog/simproc-tinytapeoutThis week, the ASIC Team submitted SimProc (Simple Processor) as a part of the TinyTapeout TTSKY25b shuttle on 10 November 2025.

TinyTapeout provides a multi-project wafer (MPW) platform where each design occupies a small tile within the final ASIC.

SimProc, along with an integrated UART-based communication interface, was implemented on a 2x2 tile (approximately 320×200 µm), with an on-chip memory size of 64 bytes (reduced from the original 256 bytes due to size limitations).

The RTL for SimProc was written in SystemVerilog and first validated on a DE10-Lite FPGA. The tapeout flow was then handled by the OpenLane/LibreLane toolchain, which automated synthesis, floorplanning, and place-and-route. Aside from adjusting configuration parameters to ensure the design fit within a 2×2 tile and met timing, the end-to-end process from RTL to ASIC was almost entirely automated.

The shuttle is now in fabrication, with chips expected to arrive in May 2026.

ASIC Technical Details

After running the design through the OpenLane/LibreLane toolchain, the TinyTapeout GitHub workflow automatically executed synthesis, place-and-route, verification, and GDS generation. The resulting reports summarize resource usage, timing, and physical layout for the final SKY130 implementation of SimProc.

Technical Specifications :

  • Recommended Clock Frequency: 30 MHz
  • Standard Cell Count: 9199 cells
  • Cell Area Usage: 59.94% of 2×2 tile
  • Total Wire Length: 158,110 µm

  • Memory: 64 bytes (implemented as flip-flops)

  • Standard Cell Breakdown:

    Cell Type Count Percentage
    Combinational 1598 17.37%
    Flip Flops 706 7.69%
    Buffers 443 4.81%
    Inverters 42 0.46%
    Fill 4068 44.22%
    Tap 1037 11.27%
    Misc 1305 14.18%
    Total 9199 100%

I/O Signal Mapping (TinyTapeout Pinout)

SimProc uses TinyTapeout’s standard 8-pin I/O structure:

  • ui[7:0]: input
  • uo[7:0]: output
  • uio[7:0]: bidirectional (we use them as inputs)

The mapping for our design is:

Pin # Input Output Bidirectional
0 uart_rx uart_tx clk_per_bit[0]
1 - halt clk_per_bit[1]
2 - done clk_per_bit[2]
3 - - clk_per_bit[3]
4 - - clk_per_bit[4]
5 - - clk_per_bit[5]
6 - - clk_per_bit[6]
7 - - clk_per_bit[7]

The UART baud rate can be configured using the 8-bit clk_per_bit input, given by the equation:

BAUD = f_clk / (4 × clk_per_bit)

I/O Summary

  • UART:
    • RX on ui[0]
    • TX on uo[0]
    • Baud rate set using uio[7:0] (clk_per_bit)
  • Status Flags:
    • halt flag on uo[1]
    • done flag on uo[2]

SimProc Design Overview

SimProc is a compact 8-bit CPU designed entirely from scratch in SystemVerilog.
Its architecture was originally introduced in my ECE243 (Computer Organization) course, where our professor designed and explained the fundamentals of SimProc. Inspired by that, I implemented the full processor in SystemVerilog and adapted it for ASIC fabrication through TinyTapeout.

The CPU features a minimalist instruction set of 11 atomic operations, supported by a 64-byte unified memory for both data and program storage.

To make the processor more interactive and extensible, I integrated a UART interface for serial communication - enabling programming, monitoring, and debugging directly over a terminal connection.
I’m also developing a C library API that provides a higher-level interface for communicating with the chip, making it easier to send instructions, read memory, and control execution from a host computer.

]]>UofT ASIC TeamClick ~Clock: Rethinking Digital Design Beyond the Clock2025-10-09T00:00:00+00:002025-10-09T00:00:00+00:00https://uoftasic.com/blog/async-circuits-workshopThis week, Vishwa Eswaran, an associate from the ASIC Team hosted a technical workshop which introduced asynchronous circuits to the larger ECE undergrad community here at UofT on behalf of the ASIC Team. The workshop was held in BA1240 from 6-8PM on October 9th, 2025.

The workshop description was:

Conventional digital design relies on a global clock - a bottleneck for speed, power, and scalability. Asynchronous (clock-free) systems replace it with local handshakes, enabling faster, leaner, and more adaptable hardware. This workshop introduces Async fundamentals and their role in AI, edge, and low-power design, showing how “click not clock” thinking is reshaping next-gen computing.

More than 40 students RSVPd to attend the workshop, which included an interactive portion to demonstrate the potential benefits of asynchronous pipelining.

The workshop slides can be found here, and an open discussion async-circuits channel can be found on our IEEE UofT Discord (Which you can find the invite for on our linktree).

We attempted to record the workshop session, unfortunately technical difficulties got the better of us and we were unable to retrieve the full recording. The first half of the workshop is on youtube, attached to this post.

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