UofT ASIC

Projects

Everything the team has designed, is designing, or has in fabrication. Status advances left to right.

All projects

2 entries

tinyCGRA

A configurable 2×2 coarse-grained reconfigurable array with serial configuration, implemented in SystemVerilog for Tiny Tapeout.

  • SKY130
  • TTSKY26b
  • 1 × 1 tile
  • 30 MHz
  • 4
Taped out

SimProc

An 8-bit processor programmable over UART, taped out on the Tiny Tapeout TTSKY25b shuttle.

  • SKY130
  • TTSKY25b
  • 2 × 2 tiles
  • 30 MHz
  • 9,199
Taped out